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1 features ? low side power mosfet output drivers - output voltage clamp (typ) . . . . . . . . . . . . . . . . 80v - maximum output current . . . . . . . . . . . . . . . . 5a/2a -output r ds(on) (t j = 150 o c) (max) . . . . . 0.57 ? /0.62 ? ? controlled slew rate switching (hip0084) ? single pulse energy rating . . . . . . . . . . . . . . . . . 70mj ? programmable output over current shutdown threshold - bit select 2a or 5a on outputs 3 and 4 ? output protection - output over current shutdown - output over voltage clamp - over temperature diagnostic feedback ? diagnostics for shorts, opens and over temperature ? synchronous serial interface with - 22-bit serial diagnostic register - spi compatible interface ? single 5v supply operation with cmos logic inputs ? supply current, i cc , full load (typ) . . . . . . . . . <10ma ?low jc power sip packages sip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 o c/w psop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 o c/w ?-40 o c to 125 o c operating temperature applications description the hip0082 and hip0084 quad power drivers contain four individually protected ndmos tr ansistor switches to drive inductive and resistive loads such as: fuel injectors, relays, solenoids, etc. the outputs are low-side switches driven by active-low cmos logic inputs . each output is protected against excessive current due to a short-circuit. internal drain-to-gate zener diodes provi de output clamping for over voltage. an integrated charge pump allows operation from a single 5v logic supply. diagnostic circuits provide ground short (sg), supply short (sc) and open load (ol) detection for each of the four output st ages and indicate over tempera - ture. diagnostic information ma y be read via a synchronous serial interface. six bits of write/store data sets a long or short ol fault delay time for each output and sets outputs 3 and 4 to a 2a or 5a current shutdown threshold. the hip0084 is specified with cont rolled slew rate switching. both types are fabricated in a power bimos ic process and are intended for use in automotiv e and other applications with a wide range of temperature and el ectrical stress. they are par - ticularly suited for driving high-current inductive loads requiring high breakdown voltage and high output current. both types available in the 15 lead power sip or 20 lead psop packages with low thermal resistance for high power applications. pinouts ?drivers for ?system use - solenoids -injectors - automotive - relays -steppers - appliances -power output -motors - industrial -lamps -displays - robotics ordering information part number temp. range( c) package pkg. no. hip0082as1 -40 to 125 15 ld sip z15.05a hip0084as1 -40 to 125 15 ld sip z15.05a HIP0082AS2 -40 to 125 15 ld sip z15.05b hip0082ab -40 to 125 20 ld psop m20.433 hip0084ab -40 to 125 20 ld psop m20.433 hip0082, hip0084 (sip) top view hip0082, hip0084 (psop w/heat slug) top view out4 out2 clk txd gnd (v ss ) v cc out1 out3 heat sink tab internally connected to pin 8 ground (v ss ) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 in4 in2 cs rst r/w in1 in3 integral copper heat sink ?slug? for pcb contact or ext. heat sink gnd (slug) in4 out4 in2 gnd (v ss ) out2 cs clk txd gnd (slug) gnd (slug) in3 out3 in1 gnd (v ss ) out1 r/w v cc rst gnd (slug) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 hip0082, hip0084 quad power drivers with serial diagnostic interface fn3643.4 preliminary may 1998 caution: these devices are sensitive to electrostati c discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright ? intersil corporation 1999
2 block diagram s r q diag. reg. reg. shift store write/ txd clk cs r/w inx rst delay filter/ filter delay i sc ref (prog. 3, 4) q o v sg 1 of 4 channels sc sg outx q ol ref ol ol reset por rst osc i olf i ol(max) v cc v cc charge pump ref ref rst over temp. v cc + - + - + - por por (short-to-gnd) (short circuit) open- load current sense q o outx sg ol sg ol hip0084 output stage d ol sc r ol (note 1) v cc v batt load note 2, note 2, case 2 case 1 v batt load v cc v ss (gnd) osc r/w notes: 1. for open-load detection, the hip0082 has an internal series pullup resistor, r ol and diode, d ol connected from outx to v cc . 2. hip0084 ol (open-load) detection: case 1: for ol detection, an external series resi stor and diode pullup connected from outx to v cc is needed. case 2: if no failure distinction for ol or sg (short-to-gnd) is required, both faul ts may be detected (without distinction), w ith an external pulldown resistor. for either case, the pullup or pulld own resistors should be typically 10k ? or greater. hip0082, hip0084
3 absolute maximum ratings t a = 25 o c thermal information supply voltage (logic and control), v cc . . . . . . . . . . . . -0.3v to 7v power mosfet drain voltage, v o (note 3) . . . . . . -0.7 to v clamp output clamp energy, e ok (see note 5) . . . . . . . . . . . . . . . . 70mj input voltage (logic and driver inputs), v in . . . -0.5v to v cc + 0.5v maximum output current, outputs 1 and 2 . . . . . . . . . . . . . . . . +2a maximum output current, outputs 3 and 4 . . . . . . . . . . . . . . . . +5a maximum total output current, all outputs on . . . . . . . . . . . . +8a maximum peak output current, i o(max) , (note 4) . . . . . -5a to i sc operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 125 o c thermal resistance (typ ical, notes 5, 6, 7) ja ( o c/w) jc ( o c/w) power sip package. . . . . . . . . . . . . . . 45 3 psop package . . . . . . . . . . . . . . . . . . 40 2 maximum junction temperature. . . . . . . . . . . . . . . -40 o c to 150 o c maximum storage temperature range, t stg . . . . -55 o c to 150 o c maximum lead temperature (during soldering 10s) . . . . . . 300 o c (psop - lead tips only) die characteristics back side potential . . . . . . . . . . . . . . . . . . . . . . . .v ss (tab ground) caution: stresses above those listed in ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditi ons above those indicated in the operational sections of this specification is not i mplied. notes: 3. the mosfet output drain is internally cl amped with a drain-to-gate zener diode that tu rns on the mosfet to hold the drain at th e v clamp voltage. refer to the electrical specifications table for the v clamp voltage limits. 4. each output has over current shutdown protection in the positi ve current direction. the maximum peak current rating is set equa l to the minimum over current shutdown as detailed in the electrical specification table. in t he event of an over current shutdown the i nput drive is latched off. the output short must be removed and the input toggled off and on to restore the output drive. 5. refer to application note an9416 for single pulse energy and devi ce dissipation rating informati on, including inductive load op eration and other thermal stress characterization. 6. ja is measured with the component mount ed on an evaluation pc board in free air. 7. maximum psop package dissipation at 125 o c with 26 o c/w heat sink (6 sq cm copper pcb) is 0.96w. electrical specifications v cc = 5v 10%, t a = -40 o c to 125 o c; unless otherwise specified parameter symbol test conditions hip0082 hip0084 units min typ max min typ max power outputs output on resistance (normal mode) r ds(on)1 , r ds(on)2 outputs 1 and 2, one output on, i out = 2a, t j = 150 o c - - 0.62 - - 0.62 ? r ds(on)3, r ds(on)4 outputs 3 and 4, one output on, i out = 2a, t j = 150 o c - - 0.57 - - 0.57 ? output on resistance (normal mode) r ds(on)1 , r ds(on)2 outputs 1 and 2, one output on, i out = 2a, t j = 75 o c n/a - - 0.5 ? output on resistance (normal mode) r ds(on)3 , r ds(on)4 outputs 3 and 4, one output on, i out = 2a, t j = 105 o c - - 0.5 ? output zener clamp voltage v z i out = 40ma 73 80 90 73 80 90 v matching zener clamp voltage ? v z i out = 40ma, t z = 100 s n/a - - 1.5 v output short current limit, outputs 1 and 2 (note 8) i sc(l) 2 - 3.4 3 - 5.1 a output short current limit, outputs 3 and 4 (note 8) i sc(l) isc bit high 2 - 3.4 2 - 3.4 a output short current limit, outputs 3 and 4 (note 8) i sc(h) isc bit low 5 - 7.5 5 - 8.3 a short circuit current filter time t sc - - 1 - - 3 s output capacitance c o v outx = 16v, f = 1mhz - - 250 - - 250 pf hip0082, hip0084
4 positive output voltage ramp slew rate, inductive load switching off sr1 i outx = 1a, load 6mh, 12 ? ; measure 25% to 75% of v z 6 70 100 6 14 24 v/ s i outx = 1a, load 6mh, 12 ? ; measure 4v to 16v of v z n/a 2 9 20 v/ s i outx = 1a, load 6mh, 12 ? ; measure 75% to 95% of v z 5.1 11 20.4 v/ s negative output voltage ramp slew rate, inductive load switching on sr2 v batt = 12v, load 6mh, 6 ? ; measure 25% to 75%, v cc = 5v 2% 0.75 15 25 0.75 1.5 3.75 v/ s v batt = 12v, load 6mh, 6 ? ; measure 25% to 75%, t j = 25 o c, v cc = 5v 2% n/a 1 - 3 v/ s output negative voltage ramp fall time t f i outx = 2a, from 90% to 10%, 6 ? load - - 25 - 15 25 s turn-off delay t d(off) i outx = 2a, from 50% of in x to 10% of outx 0.5 - 3 - - 10 s turn-on delay t d(on) i outx = 2a, from 50% of in x to 90% of outx n/a - - 10 s matching turn-on delay ? t d(on) - - 3 s matching turn-off delay ? t d(off) - - 3 s output rise time t r for sr3 postive ramp conditions from 10% to 90% of v z - 10 s output leakage current i lk inx = high, v outx = 60v - - 10 n/a a v outx = 60v, v cc open - - 10 a inx = high, v outx = v cc+ to 60v n/a -10 - 10 a inx = low, v outx = 0v to 60v, v cc = 0v -10 - 10 a supply power supply current i cc standby, no load - 7.5 15 - 7.5 15 ma low v cc shutdown thresh - old v cc(low) (note 9) 3.4 3.7 4.0 3.4 3.7 4.0 v active supply range for rst pin v cc(rst) 3.5 - 5.5 3.5 - 5.5 v inputs ( inx , cs , clk, rst , r/ w , txd) low-level input voltage v il -0.3 - 0.2 x v cc -0.3 - 0.2 x v cc v high-level input voltage v ih 0.7 x v cc - v cc + 0.3 0.7 x v cc - v cc + 0.3 v input hysteresis voltage v hys 0.85 1.2 2.25 0.85 1.2 2.25 v reset time after rst l h t rst 48 - 80 48 - 80 s input pull-up resistance r in 50 - 150 50 - 150 k ? input current i ih logic high input voltage - - 2 - - 2 a txd pin (r/ w = high) three-state leakage current i lk_txd cs = high, v txd = v cc -5 - 5 -5 - 5 a logic high output voltage v txdh i oh = -4ma, cs = low v cc - 0.4 - - v cc - 0.4 - - v logic low output voltage v txdl i ol = 3.2ma, cs = low - - 0.42 - - 0.42 v electrical specifications v cc = 5v 10%, t a = -40 o c to 125 o c; unless otherwise specified (continued) parameter symbol test conditions hip0082 hip0084 units min typ max min typ max hip0082, hip0084
5 open load detection output on resistance in high r ds(on) open-load detection mode r ds(on)1ol r ds(on)2ol outputs 1 and 2, one output on, i out = 10ma, t j = 150 o c - - 6.2 n/a ? r ds(on)3ol r ds(on)4ol outputs 3 and 4, one output on, i out = 10ma, t j = 150 o c - - 5.7 ? max. output current in high r ds(on) mode i ol(max) 90 - 180 ma min. output current in low r ds(on) normal mode (hysteresis range) i o(hys) 0.25 x i ol (max) - 0.95 x i ol (max) na ma open-load fault threshold i olf (isc bit is set in fault register) 3 - 20 15 60 100 ma open-load detection pull-up resistance r ol 2 - 6.5 na k ? open-load delay time after inx h l t doll td_olx bit = low 3 - 5.2 3 - 5.2 ms open-load delay time after inx h l t dolh td_olx bit = high (note 10) 340 - 580 340 - 580 s open load filter time t ol 150 - 252 150 - 252 s over temperature and short circuit protection over temperature detection threshold t tmp 155 - 165 155 - 165 c output short-to-gnd threshold v sg 2.4 - 2.9 2.4 2.6 2.9 v short-to-gnd filter time t sg 150 - 252 150 - 252 s serial interface (figure 3) c ext = 50pf serial clock frequency f clk 50% duty cycle - - 3 - - 3 mhz propagation delay clk to data valid t pclkdv - - 150 - - 150 ns setup time, cs to clk t cslclk 150 - - 150 - - ns cs low to data valid t csldv - - 100 - - 100 ns hold time cs after clk t clkcsh 150 - - 150 - - ns cs high to output high z t cshdz - - 100 - - 100 ns minimum time clk = high t clkh 100 - - 100 - - ns minimum time clk = low t clkl 100 - - 100 - - ns setup time r/ w low to clk t rwlclk 150 - - 150 - - ns r/ w low to output high z t rwldz - - 100 - - 100 ns setup time data valid to clk low t dvclkl 20 - - 20 - - ns setup time r/ w high to clk t rwhclk 100 - - 100 - - ns time r/ w high to data valid t rwhdv - - 100 - - 100 ns notes: 8. each output has over current shutdown protection in the positiv e current direction. the maximum peak current rating is set equa l to the minimum over current shutdown as detailed in the electrical specification table. in t he event of an over current shutdown the i nput drive is latched off. the output short must be removed and the input toggled off and on to restore the output drive. 9. the ?low v cc shutdown? is an internal control that switches off all power drive stages when v cc is less than v cc(low) . 10. measurement includes the filter time. electrical specifications v cc = 5v 10%, t a = -40 o c to 125 o c; unless otherwise specified (continued) parameter symbol test conditions hip0082 hip0084 units min typ max min typ max hip0082, hip0084
6 functional description power output stages the block diagram details the equivalent logic control of each power output driver. each power output stage has a separately controlled input with hysteresis and is active low with a pull-up to maintain an off state when there is no input. each output driver has sensors for short circuit, open load and short-to-ground fault detect ion. the drive to each output is also controlled by the por, reset and an rs latch that switches off the output when a short circuit occurs. an inter - nal zener diode feedback from t he drain to gate of the output driver provides over voltage clamp protection. for the hip0082, each power output channel has a low r ds(on) (q o ) and a high r ds(on) (q ol ) ndmos drivers in par - allel. the high r ds(on) driver is used to enhance the open load detection while providing one-tenth of the output load current. the hip0084 output is modified into one low r ds(on) driver and provides controlled slew rate switching. in addition, the hip0084 requires an external zener and resistor network for ol detection. refer to the block diagram, specifications and ol detection information. reset operation an active low reset on the rst pin or the writing of a low to the test bit is required to guarantee normal operation after power-up. when rst is in the low state all outputs are off and all registers and counters are reset. when the reset pin is taken high the ic remains in reset mode for a time t rst . when the rst pin is switched active low, the on-chip reset circuitry ensures that the out put stages are turned off, all counters and registers are reset, and the programmable functions are in their default st ates. the default state for the test bit is a low. the default state for the short-circuit cur - rent for outputs 3 and 4 is the higher value for 5a maximum current operation (isc bit low). the default state for the open-load delay times for each output is the higher value between 3ms and 5.2ms (td_olx bits low). low power drive shutdown as part of the por function, there is a low voltage power drive shutdown when the supply voltage, v cc drops below the voltage threshold, v cc(low) . during the low voltage condition the output stages are held off. over voltage clamp operation a drain-to-gate zener diode on each output driver internally clamps an over voltage pulse, including the kick pulse gen - erated when turning off an inductive load. while providing over voltage protection, it is not part of the diagnostic feed - back via the diagnostic register. short-circuit (sc) protection if the output current is above t he current limit for a time delay greater than t sc the output is switched off and the corre - sponding bit in the diagnostic register set. the current level for shutdown on outputs 3 and 4 is programmable between 2a and 5a with the isc bit. after shutdown, the output remains off until the corresponding input is taken high and again low. open-load (ol) detection load currents are monitored whil e the outputs are on. if the open load current falls below the fault threshold current, i olf , the open load fault bit is set after a delay time t dol . the open load fault bits (olx) are stored in the diagnostic register as shown in figur e 1. the output of open-load detector circuit is input to the diagnostic register via the delay filter and is also connected directly to the r/ w shift register for potential monitoring via the serial interface. for the hip0082 in an on state, if a load current falls below the i ol threshold level, a low load current condition is detected and the low r ds(on) , high current dmos output transistor (q o ) is switched off. the high r ds(on) driver (q ol ) continues to conduct. if the load current is then increased from a low level, q o will be switched on, with hys - teresis, to a normal mode of operation as defined by the i ol(hys) limits. when the output current is higher than i ol(max) , both q o and q ol conduct. the hip0084 ol detection diagnostics differ from the hip0082. the hip0084 does not have an internal pullup resistor (shown in the bloc k diagram of the hip0082 as r ol in series with the diode, d ol ) connected between outx and v cc . where no failure distinction between an ol and a sg fault condition is required, an external pulldown resistor from outx-to-ground may be used. for a distinction between an ol and sg fault condition, an external pullup resistor in series with a diode between outx and v cc is needed. the pullup resistor must have a value greater than (v cc - v be - v sg )/i olf where v cc is the external power supply voltage for the outputs, v be is the diode drop of the series diode; v sg is the short-to- ground comparator threshold level for outx and i olf is the open-load current detection threshold of outx. while the values for pullup and pulldown resistors are not critical, they should not be minimally small. in either case, they should be typically 10k ? or greater. output short-to-gro und (sg) detection when the voltage on an output pin is below v sg and the output is off, a ground short is detected and stored in the diagnostic register after a delay t sg . the outputs of the short-to-ground (sg) compar ators are also connected directly to the diagnostic regist er so that they can be moni - tored via the serial interface. where v sg is specified in the range of 2.4v to 2.9v, i olf is specified in the range of 15ma to 100ma for the hip0084 and 3ma to 20ma for the hip0082. serial interface operation microprocessor communication to the diagnostic/control reg - isters is via a 4 wire serial interface. data control is bidirec - hip0082, hip0084
7 tional, the direction of data transfer being dependent on the state of the r/ w pin (see figure 2). diagnostic read operation when cs goes from high to low (while clk is high), data from the diagnostic register is jammed into the serial shift register, at the same time, t he txd pin exits three-state and outputs the fsb bit which indicates whether any of the fault bits in the shift register are set. with the first negative transi - tion of clk, the diagnostic regist er is cleared. data from the shift register is shifted to tx d on each low to high transition of the clk pulse. the diagnostic fault bits as shown in figure 1 are described as follows: fsb bit - indicates that one or more of the bits in the diagnostic register are set. tmp bit - indicates that the chip temperature has exceeded the limit t tmp . the outputs are not switched off when this occurs; the condition is indica ted by the setting of the tmp bit. sensors for the tmp bit are located near the power drivers and are ored to provide a single bit for the chip. scx bits - indicate a short-circuit to battery or over current on the corresponding output. the corresponding output driver has been latched off. it will remain off until the input is toggled off and then on. olx bits - indicate that no load (or a high resistance load) is connected to the corresponding output. the open load bit is set when the output current is less than i olf . sgx bits - indicate that the voltage on the corresponding output is below the v sg limit. the final 8 bits (most significant bits) of the diagnostic word indicate the states of the open load and short-to-ground comparators when the cs pin went from high to low. as such, an external microprocessor can monitor the status of the ol and sg comparators di rectly to cross-check the action of the filtered fault bi ts, ol1 to ol4 and sg1 to sg4 (see figure 1). the action of t he filters is to suppress switch - ing anomalies that may be read as false data. to avoid potential confusion in normal operation, reading the direct comparator output bits is not necessary or recommended. diagnostic write operation when the r/ w pin is in the low state it is possible to write six bits to the write/store register to influence the ic mode of operation. the write operation is illustrated in figure 3. the fsb (first significant bit) is present when cs pin goes from high to low while the clk pin is high and the r/ w pin is in the high (read) state. the fsb is the error flag and is the same fsb bit shown for the figure 1 read operation. when fsb is high, a read operation is assumed, until or unless the r/ w goes low. when the r/ w pin goes low (write mode), txd is ready to receive input dat a. the first write bit occurs when clk goes low. in the write mode, data is latc hed in the write/store register when cs goes high. the write/st ore data will be in the default state after a rst reset or power up reset. the write operation does not affect the data present in the diagnostic register and a read operation does not affect the data present in the write/store register. the programmable bits in th e write/store register are: test bit - used to put the ic in test mode (not recom - mended). this bit should be low for normal operation. isc bit - this bit programs the short circuit level for outputs 3 and 4. when this bit is set high the lower value for the cur - rent shutdown threshold is set. td_olx bits - the t dol delay times for the td_olx bits are programmable to two levels (t doll or t dolh ). these bits set the delay times for the open-load detection at each of the four outputs. a logical high sets the open-load delay time to its shorter value. reading serial data on the spi interface when interfacing to an 8-bit spi system and choosing to read all 22 bits as shown in figure 1, note that the fsb (first significant bit) is the first bit present before the first clk pulse goes low. this leaves 21 bits of available output data to be shifted by the clk. an fsb high state when cs goes low indicates the presents of a fault bit in the diagnostic register. the fsb bit is nor - mally used as a flag to initiate a read of all data bits in the shift register. the fsb output bit should be separately directed to an interrupt or port that is programmed to initiate a fault data read sequence. direct comparator outputs clk cs r/w txd zz = high impedance zzzz fsb tmp sc1 ol1 sg1 sc2 ol2 sg2 sc3 ol3 sg3 sc4 ol4 sg4 ol4 ol1 ol2 ol3 sg4 sg1 sg2 sg3 zz figure 1. serial interface read operation hip0082, hip0084
8 since spi data is read 8 bits at a time, reading 24 bits leaves 3 (dummy) bits that follow after the 21 bits of diagnostic fault output data. internally, the shift register has an input low state which will cause the last 3 bits shifted out to be low. there is no need in normal operation to read the direct comparator output bits, except to directly read the fault state when cs goes low or to cross-check on the filtered ol and sg fault data. if the direct comp arator data is ignored, then only 16 bits of spi data is read. in this case the last 3 bits in the 16 bit sequence is the first 3 bits of direct comparator data which can be ignored. data read from a spi interface starts with the first clock pulse. the cs and r/ w inputs cannot be changed while reading data from the shift regi ster. and, as noted, an inter - nal low on the shift register input causes low data bits to fol - low the 21 bits of diagnostic data. while the write/store operation ca lls for 6 bits of data, a spi write will output 8 bits. the first 2 bits transmitted should be dummy bits. the 3-bit is the test bit which should be low for normal operation. the test bit is used to facilitate testing in the manufacturing process and is not recommended for other use. the 6 programmable bits are described in the section on diagnostic write operation. pin descriptions v cc and gnd - 5v supply and ground connections. a charge pump is used to boost the power mosfet gate drive. this allows a single 5v supply to satisfy all logic and drive requirements. out1 - out4 - low-side output drivers with 0.62 ? (out1 and out2) or 0.57 ? (out3 and out4) on resistance. the outputs are provided with over current shutdown and over voltage clamping. additional ly, open-load and short-to- ground detection is carried out when the outputs are on. in1 - in4 - active-low cmos logic inputs which control the output stages out1 - out4. these inputs are provided with pull-up resistors. rst - active-low logic-level reset input with internal pull-up resistor. clk - clock input for synchronous serial interface with inter - nal pull-up resistor. this input must be high when cs transi - tions from high to low. cs - active-low chip select input for seri al interface. this input has an internal pull-up resistor. r/ w - read/write control pin for se rial interface. this input controls whether the txd pin is an input or output. this input has an internal pull-up resistor. txd - bidirectional data pin for serial interface. when r/ w is high diagnostic data can be read from hip0082. when r/ w is low, 6 bits may be written to the internal program register. figure 2. serial interface timing diagram clk cs r/w txd f clk t clkl t clkh zzzzz zz t csldv t rwlclk t cslclk t rwldz t dvclkl t rwhdv t pclkd t rwhclk t cshdz t clkcsh zz = high impedance figure 3. serial interface write operation cs r/w txd zzzz fsb t d _ol1 t d _ol2 t d _ol3 t d _ol4 test isc zzzz clk hip0082, hip0084
9 hip0082, hip0084 power small outline plastic package (psop) e2 1 2 3 d2 e 1.10 max. x 45 o 2 places 2 places d1 0.25 cb m as s e1 -b- e3 n (datum pin 1 plane a) marker d b seating a 0.25 ca m b s s -c- -a- a1 see detail "a" a2 c 0.10 section "b-b" b b 1 c 1 c 3.10 ref. seating plane detail "a" b b 0-8 o 1.60 ref. gauge l 0.15 ref. a3 heat plane slug l1 plane -h- e m20.433 20 lead power small outline plastic package symbol inches millimeters notes min max min max a 0.122 0.142 3.10 3.60 - a1 0.004 0.012 0.10 0.30 - a2 0.118 0.130 3.00 3.30 - a3 0.000 0.004 0.00 0.10 - b 0.016 0.021 0.40 0.53 6, 7 b1 0.016 0.020 0.40 0.50 6, 7 c 0.009 0.013 0.23 0.32 7 c1 0.009 0.011 0.23 0.29 7 d 0.622 0.630 15.80 16.00 3 d1 0.496 0.512 12.60 13.00 - d2 - 0.043 - 1.10 - e 0.547 0.571 13.90 14.50 - e1 0.429 0.437 10.90 11.10 4 e2 - 0.114 - 2.90 - e3 0.228 0.244 5.80 6.20 - e 0.050 bsc 1.27 bsc - l 0.031 0.043 0.80 1.10 5 l1 0.014 bsc 0.35 bsc - n20 20 - rev. 0 3/96 notes: 1. dimensioning and tolerancing per ansi y14.5m - 1982. 2. "c" is a reference datum . seating plane is defined by lead tips only. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. d measured at -h-. 4. dimension e1 does not include interlead flash or pro- trusion. interlead flash or protrusion shall not exceed 0.15 per side. e1 measured at -h-. 5. dimension "l" is the length of terminal for soldering to a substrate. 6. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the lead width dimension at maximum material condition. 7. section "b-b" to be determined at 0.10mm to 0.25mm from the lead tip. 8. controlling dimension: millimeter. 9. dimensions conform with jedec outline mo-166aa issue b. 17.15 land pattern n 1 13.92 4.22 1.52 0.71 2.87 e 7.26 4.09 2.21 4.09
10 hip0082, hip0084 single-in-line plast ic packages (sip) d see tab detail e1 terminal #1 terminal n e a l1 l f typ all leads tab detail r1 -y- -z- 3 e 2 -x- e 1 e b 0.010(0.25) z x m m y m 0.024(0.61) z m c e2 ?p ? 0.015(0.38) z x m s notes: 1. refer to series symbol list, jedec publication no. 95. 2. dimensioning and tolerancing per ansi y14.5m-1982. 3. n is the number of terminals. 4. controlling dimension: inch. hl h h h h h h h h l l l l l l l e 3 z15.05a (jedec mo-048 ab issue a) 15 lead plastic single-in-line package staggered vertical lead form symbol inches millimeters min max min max a 0.172 0.182 4.37 4.62 b 0.024 0.031 0.61 0.79 c 0.014 0.024 0.36 0.61 d 0.778 0.798 19.76 20.27 e 0.684 0.694 17.37 17.63 e1 0.416 0.426 10.57 10.82 e2 0.110 bsc 2.79 bsc e 0.050 bsc 1.27 bsc e1 0.200 bsc 5.08 bsc e2 0.169 bsc 4.29 bsc e3 0.700 bsc 17.78 bsc f 0.057 0.063 1.45 1.60 l 0.150 0.176 3.81 4.47 l 1 0.690 0.710 17.53 18.03 n15 15 ?p 0.148 0.152 3.76 3.86 r1 0.065 0.080 1.65 2.03 rev. 1 4/98
11 hip0082, hip0084 single-in-line plast ic packages (sip) notes: 1. dimensioning and tolerancing per ansi y14.5m - 1982. 2. n is the number of terminals. 3. all lead surfaces are within 0. 004 inch of each other. no lead can be more than 0.004 inch above or below the header plane, ( datum). 4. controlling dimension: inch. d e1 r1 e -y- e 3 0.010 z x m s y m b typ 15 lead tips 0 o - 8 o header bottom 0.004 0.008 z 15 e2 e f a -x- -z- c (note 3) surfaces l l1 ?p bottom view 0.814 0.407 of 0.150 c l 0.130 0.700 0.774 0.662 0.030 typ 0.050 typ 0.350 0.700 land pattern z15.05b 15 lead plastic single-in-line package surface mount ?gullwing? lead form symbol inches millimeters min max min max a 0.172 0.182 4.37 4.62 b 0.024 0.031 0.61 0.79 c 0.018 0.024 0.46 0.61 d 0.778 0.798 19.76 20.27 e 0.684 0.694 17.37 17.63 e1 0.416 0.426 10.57 10.82 e2 0.110 bsc 2.79 bsc e 0.050 bsc 1.27 bsc e3 0.700 bsc 17.78 bsc f 0.057 0.063 1.45 1.60 l 0.065 0.080 1.66 2.03 l1 0.098 0.108 2.49 2.74 n15 15 ?p 0.148 0.152 3.76 3.86 r1 0.065 0.080 1.65 2.03 rev. 1 11/97 -z-

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